Design recipes for FPGAs : using Verilog and VHDL / Peter Wilson.
Record details
- ISBN: 9780080971292
- Physical Description: xix, 369 páginas : ilustraciones ; 24 cm.
- Publisher: London, UK : Elsevier, 2007.
- Copyright: ©2016.
Content descriptions
| Bibliography, etc. Note: | Incluye bibliografía e índice. |
| Immediate Source of Acquisition Note: | IPICYT ; Compra por proyecto/Dr. Elías Razo Flores/FORDECYT-S-3936/R.792 ; 2016. |
| Language Note: | En inglés. |
Search for related items by subject
| Subject: | VHDL (Lenguaje descriptivo de hardware). Verilog (Lenguaje de descripción para computadora). |
Available copies
- 0 of 1 copy available at IPICYT.
Holds
- 0 current holds with 1 total copy.
Show Only Available Copies
| Location | Call Number / Copy Notes | Barcode | Shelving Location | Status | Due Date |
|---|---|---|---|---|---|
| Biblioteca Ipicyt | TK7885.7W5 D4 2016 | ECO00587 | Coleccion General | Proyecto | - |
| LDR | 00620nam a2200205zi 4500 | ||
|---|---|---|---|
| 001 | 43140 | ||
| 003 | CONS | ||
| 005 | 20160526202439.0 | ||
| 007 | ta | ||
| 008 | 000000t20162016enka fr #001 0#enk d | ||
| 020 | . | ‡a9780080971292 | |
| 040 | . | ‡bspa ‡erda | |
| 041 | 0 | . | ‡aeng |
| 050 | 0 | 0. | ‡aTK7885.7 ‡bW5 D4 2016 |
| 100 | 1 | . | ‡aWilson, Peter. |
| 245 | 1 | 0. | ‡aDesign recipes for FPGAs : ‡busing Verilog and VHDL / ‡cPeter Wilson. |
| 264 | 1. | ‡aLondon, UK : ‡bElsevier, ‡c2007. | |
| 264 | 4. | ‡c©2016. | |
| 300 | . | ‡axix, 369 páginas : ‡bilustraciones ; ‡c24 cm. | |
| 336 | . | ‡atexto ‡btxt ‡2rdacontent | |
| 337 | . | ‡asin medio ‡bn ‡2rdamedia | |
| 338 | . | ‡avolumen ‡bnc ‡2rdacarrier | |
| 504 | . | ‡aIncluye bibliografía e índice. | |
| 541 | 0 | . | ‡fIPICYT ; ‡cCompra por proyecto/Dr. Elías Razo Flores/FORDECYT-S-3936/R.792 ; ‡d2016. |
| 546 | . | ‡aEn inglés. | |
| 650 | 0. | ‡aVHDL (Lenguaje descriptivo de hardware). | |
| 650 | 0. | ‡aVerilog (Lenguaje de descripción para computadora). | |
| 901 | . | ‡a43140 ‡b ‡c43140 ‡tbiblio ‡sSystem Local | |
